Hardware Verification


As part of the detailed design phase (phase 4) you are required to design the Safety Instrumented System (SIS) in accordance with the Safety Requirements Specification (SRS) so that the Safety Integrity Level requirements (SIL) can be met.

Part of meeting these requirements is that the Hardware utilised must be able to operate and be maintained to meet the requirements of the pre-defined integrity for the determined risk reduction factor.  However, it must be noted that a purely hardware calculation will not cover the systematic targets to allow for the SIL requirements to be met.

A rigorous set of inspections to ensure that the equipment used is the equipment that has been assessed, must be conducted to ensure that the hardware verification is accurate and suitable.


As part of the Hardware Verification all components of the Safety Instrumented Function (SIF), which includes all of the sensors, barriers, logic solvers (relays), actuator, valves and any applicable common cause failures (Beta Factor) are (must be) calculated so that they meet the probability of failure on demand (PFDAVG) for a demand SIF or the probability of failure an hour (PFHAVG) for a high/continuous demand scenario.

Depending on how the client has calculated the probability of failure a different methodology is used to verify that the equipment used meets the required level defined in the SRS.  The usual methodologies utilised by ProSalus for conducting hardware verification are the Event Space Method, Reliability Block Diagrams, ISA simplified formula, Quantified Fault Tree, however, we have tools to calculate using other methodologies when specifically required by client requirements.


ProSalus regularly assists our clients in conducting hardware verification during the design or modification of SIFs. We have also conducted hardware verification for clients upon request from regulatory bodies to justify the values they have produced following their own calculations and methodologies.